Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-08-03
2008-11-04
Chaudhari, Chandra (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S248000, C257SE21652
Reexamination Certificate
active
07445986
ABSTRACT:
Memory cells with vertical transistor and capacitor and fabrication methods thereof. The memory cell comprises a substrate with a trench. A capacitor is disposed at the bottom of the trench. A first conductive layer is electrically coupled to the capacitor. The first conductive layer is isolated the substrate by a collar dielectric layer. A trench top oxide (TTO) layer is disposed on the first conductive layer. A vertical transistor is disposed over the TTO layer. The vertical transistor comprises a gate dielectric layer disposed on the sidewalls of the upper portion of the trench, and a metal gate disposed in the upper portion of the trench.
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Chaudhari Chandra
Nanya Technology Corporation
Quintero Law Office
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