Memory cell with plasma-grown oxide spacer for reduced DIBL...

Details Memory cell with plasma-grown oxide spacer for reduced DIBL... Memory cell with plasma-grown oxide spacer for reduced DIBL...

2006-12-19

2006-12-19

Fourson, George R. (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S201000, C438S303000, C438S305000, C438S306000, C438S593000

Reexamination Certificate

active

07151028

ABSTRACT:
According to one exemplary embodiment, a method for fabricating a floating gate memory cell on a substrate comprises a step of forming a first spacer adjacent to a source sidewall of a stacked gate structure, where the stacked gate structure is situated over a channel region in the substrate. The method further comprises forming a high energy implant doped region adjacent to the first spacer in a source region of the substrate. The method further comprises forming a recess in the source region, where a sidewall of the recess is situated adjacent to a source of the floating gate memory cell, and where forming the recess comprises removing the first spacer. The method further comprises forming a second spacer adjacent to the source sidewall of the stacked gate structure, where the second spacer extends to a bottom of the recess, and where the second spacer comprises plasma-grown oxide.

REFERENCES:
patent: 2005/0064655 (2005-03-01), Kim et al.
patent: 2005/0087796 (2005-04-01), Jung
patent: 2005/0164450 (2005-07-01), Fang et al.
patent: 2006/0035431 (2006-02-01), Fang et al.

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