Memory cell structure for semiconductor memory device and fabric

Details Memory cell structure for semiconductor memory device and fabric Memory cell structure for semiconductor memory device and fabric

1996-12-24

1999-04-27

Chang, Joni

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438253, H01L 218242

Patent

active

058973508

ABSTRACT:
A memory cell structure for a semiconductor memory device and fabricating method thereof, which is suitable for DRAM memory devices of 256M or more capacity requiring a very high degree of integration, which comprises the steps of forming sequentially first and second random layers on a semiconductor substrate; patterning a first photoresist layer having a limited line width on the second random layer; patterning the second random layer using as a mask the patterned first photoresist layer; removing the first photoresist layer, and then patterning the second photoresist layer having the limited line width between the pattern of the second random layer; patterning the first random layer using as a mask the second photoresist layer which is so patterned so as to be placed between the pattern of the second random layer; and removing the second random layer and the second photoresist layer.

REFERENCES:
patent: 5091761 (1992-02-01), Hiraiwa et al.
patent: 5140389 (1992-08-01), Kimura et al.
patent: 5776825 (1998-07-01), Suganaga et al.
patent: 5792687 (1998-08-01), Jeng et al.
patent: 5798289 (1998-08-01), Ajika et al.

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