Memory cell of the EEPROM type having its threshold adjusted...

Details Memory cell of the EEPROM type having its threshold adjusted... Memory cell of the EEPROM type having its threshold adjusted...

1999-10-29

2001-12-11

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S276000

Reexamination Certificate

active

06329254

ABSTRACT:

TECHNICAL FIELD
This invention relates to a memory cell of the EEPROM type, in particular of the FLOTOX EEPROM type, having its threshold adjusted by implantation, and to a method of fabricating it.
BACKGROUND OF THE INVENTION
As is well known, the use of non-volatile memories of the EEPROM type as data storage devices is expanding by virtue of a specific feature of such memories whereby the information contained in the individual memory cells can be modified electrically in use, at both the writing and the erasing phases, in an independent, selective manner. For that purpose, a selection transistor is associated in series with each cell.
Consistently with today's technology, such storage devices rate very high in terms of reliability.
Concurrently therewith, there is a persistent demand for high capacity (at least 256 Kb) storage devices, incorporating an ever larger number of cells per memory unit. In this direction, the technology of electronic semiconductors is moving toward ever larger integration scales, and an attendant reduction in component size. This involves, however, a more critical control of their characteristics, and increased difficulty to ensure reliable performance of such advanced cells fabricated to a very large scale of integration (ULSI).
Typically, non-volatile memory cells are integrated in a substrate of a semiconductor material and laid into rows and columns to form a matrix of cells. The cell element wherein the information is stored is a MOS transistor of the floating gate type. The logic state, or level, of the cell is defined by the amount of charge contained in the floating gate of the transistor.
In particular, the amount of charge is altered in EEPROMs by causing charges to flow by tunnel effect (known as Fowler-Nordheim current) through a thin layer of silicon oxide, the so-called tunnel oxide, which intervenes between the substrate of semiconductor material and the floating gate of the transistor.
Of the various types of EEPROMs, reference will be made here to those having two levels of polysilicon. Their associated memory cells comprise each a floating gate of polysilicon overlying a layer of gate oxide which is formed on top of a silicon substrate, and a control gate, also of polysilicon, overlying the floating gate and being isolated from the latter by a so-called interpoly dielectric layer.
The selection transistor associated with a cell can be variously constructed; for example, it consists of either a single layer of polysilicon or two superposed layers of polysilicon provided above a gate oxide, with an interpoly dielectric layer optionally interposed. Where no interpoly dielectric is provided, it becomes known as a short-circuited double polysilicon construction. Where the interpoly dielectric is provided, a short-circuit must be established all the same between the two layers in appropriate areas of the device, either outside or inside the memory matrix.
In addition, circuitry transistors are usually provided in the device which may have a single polysilicon or double polysilicon, and no interpoly dielectric layer. This specification makes reference in particular to the last-mentioned instance, by way of example.
The aforementioned storage structures can be fabricated with technologies that provide for alignment of the control gate to the floating gate. Examples of such processes can be found in US Patent US-4,719,184 and European Patent EP-0255159.
One widely employed structure of EEPROM cells with a double level of polysilicon, known as FLOTOX, provides for the floating gate to be extended laterally outside the tunnel oxide region.
A single memory cell of the FLOTOX type with a double level of polysilicon formed by a standard technique is described in US Patents U.S. Pat. No. 5,793,673 and U.S. Pat. No. 5,792,670, for example. A cross-sectional view of this is given in FIG.
1
.
By way of example only, the cell is made with CMOS technology.
Referring to this Figure, the memory cell, generally referenced
1
, comprises a series of a floating gate transistor
2
and a selection transistor
3
, both of the MOS type, represented in an active area region of a substrate
4
having a first type of conductivity. The cross-section is taken in a parallel direction to the matrix columns, in particular along a source/drain line of the matrix of cells.
The floating gate transistor includes a tunnel oxide region
5
surrounded by a layer
6
of gate oxide. An overlying first layer
7
of polysilicon forming the floating gate, and a second layer
8
of polysilicon forming the control gate, are isolated electrically by an interpoly dielectric layer
9
. The latter is usually a triple layer of oxide
itride/oxide, or ONO, optionally overlaid with a thin layer of polysilicon, the so-called “polino”. A low-resistivity silicide layer, not shown in the Figure, is usually provided on top of the second polysilicon layer
8
.
The selection transistor
3
similarly includes a gate dielectric
11
which is overlaid by the first and second polysilicon layers
7
and
8
, with the interpoly dielectric layer
9
lying therebetween.
Source and drain active regions of both transistors, having a second type of conductivity, are shown at
12
,
13
and
14
. In the storage transistor
2
, they define a channel region
15
that includes specifically a tunnel area
15
′ underlying the tunnel oxide region
5
. These memories further requires a doped continuity region
16
with a second type of conductivity which is typically formed by implantation, known as the capacitor implant, and extends from the tunnel area to over the drain region
13
to ensure electrical continuity between the substrate region lying beneath the tunnel oxide (tunnel area
15
′) and the drain region
13
of the cell during its operation.
As can be seen in the Figure, the two polysilicon layers are aligned along the source/drain direction in both the floating gate transistor
2
structure and that of the selection transistor
3
.
Referring to
FIGS. 2-5
, some steps are illustrated therein of a CMOS process which adopts a so-called DPCC (short-circuited double poly) flow for making a memory cell of the EEPROM type and a transistor of the external circuitry to the matrix, as is known in the art. It should be noted that both high-voltage or HV transistors, i.e., transistors capable of sustaining high voltages, and low-voltage or LV transistors, i.e., transistors operated at relatively low voltages, are typically formed in the circuitry. They distinguish themselves by the thickness of their gate oxide layer. However, a generic transistor, representing either an LV or a HV transistor, is shown by way of example in the drawings.
The drawings are cross-sectional views taken along the same section line as indicated in FIG.
1
.
After defining the active areas, the substrate
4
is grown gate oxide layers
17
and
11
thereon, in the regions of the transistors of the circuitry
20
and the selection transistors
3
, as well as a gate oxide layer
6
in the region of the storage transistor
2
. Also defined is the tunnel oxide region
5
at the floating gate to be formed. The first polysilicon layer
7
is deposited and doped by implantation (FIG.
2
). It is then partially defined using a mask apertured at the region
2
in planes outside the drawings and not represented.
The interpoly dielectric layer
9
and a thin polysilicon layer
21
are then deposited. The last-mentioned layer provides protection for the underlying interpoly dielectric during the next masking step. At this stage, as shown in
FIG. 3
, a selective etching step is carried out to remove the thin polysilicon layer
21
and the underlying interpoly dielectric layer
9
, in those regions of the storage device where the external circuitry is to be formed, using a mask
22
which leaves the portion destined for the cell matrix covered. More generally, this mask covers the device regions intended to accommodate circuit elements with a DPCC structure.
The following step, not illustrated, includes implanting the transisto

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