LandOfFree - US Patents - Listing for Error detection/correction and fault detection/recovery

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Scan testing system for circuits under test

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Scan testing using scan frames with embedded commands

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Scan tests tolerant to indeterminate states when employing...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Scan verification for a scan-chain device under test

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Scan-based testing of devices implementing a test clock...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Scan-bypass architecture without additional external latches

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Scan-enabled method and system for testing a system-on-chip

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Scan-path circuit, logic circuit including the same, and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Scan-path flip-flop circuit for integrated circuit memory

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Scanable latch circuit and method for providing a scan...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Scanable R-S glitch latch for dynamic circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Scannable state element architecture for digital circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Scanned memory testing of multi-port memory arrays

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Scanning a protocol signal into an IC for performing a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Scanning device and method for hierarchically forming a scan pat

Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment

Scanning memory device and error correction method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Scanning reassigned data storage locations

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability

Scheduling framework for a heterogeneous computer network

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability

Scheduling method and apparatus for a distributed automated test