Usage of redundancy data for displaying failure bit maps for...

Use of a scan chain for configuration of BIST unit operation

Use of ECC with iterative decoding for iterative and...

User available body scan chain

User equipment using hybrid automatic repeat request

Using bit errors from memory to alter memory command stream

Using clock gating or signal gating to partition a device...

Using data compression for faster testing of embedded memory

Using error checking bits to communicated an address or...

Using hardware or firmware for cache tag and data ECC soft...

Using microcode to correct ECC errors in a processor

Using profiles to perform Bit Error Rate Testing

Using profiles to perform bit error rate testing

Using quadrant shifting to facilitate binary arithmetic with...

Using SAM in error correcting code encoder and decoder...

Using statistical signatures for testing high-speed circuits

Utilizing multiple bitstreams to avoid localized defects in...

Utilizing multiple test bitstreams to avoid localized...

Utilizing multiple test bitstreams to avoid localized...

Utilizing multiple test bitstreams to avoid localized...