Using hardware or firmware for cache tag and data ECC soft...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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Details

C714S005110, C714S010000, C712S220000

Reexamination Certificate

active

06802039

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of computer systems and, more specifically, the present invention relates to a method of error corrections.
2. Description of the Related Art
Scaling technology improves overall system performance by increasing transistor density and reducing power consumption. Increasing transistor density, however, also increases soft (or transient) errors. A soft error occurs when a logical value of a memory cell or a logic element is erroneously changed to the opposite logical value as a result of cosmic radiation and/or alpha particle bombardment. Future process technology will enable more and more devices with finer geometry to be packed on a single die. This trend will increase the soft error rate significantly.
Storage elements in a microprocessor are sensitive to soft errors. To improve processor performance, modern processors are often built with on-chip caches. With increasing integrated circuit density, on-chip caches are increasingly sensitive to these soft errors. Thus, soft errors may corrupt logic values or data stored in the caches, which may affect the correct operation of the system. In the past, soft errors are typically left unprotected because they are difficult to protect and were not as severe a problem. With more advanced scaling technology, these soft errors can no longer be ignored.


REFERENCES:
patent: 5274799 (1993-12-01), Brant et al.
patent: 5381544 (1995-01-01), Okazawa et al.
patent: 6327690 (2001-12-01), Zhang et al.
patent: 6625749 (2003-09-01), Quach

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