Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
Reexamination Certificate
2005-09-27
2005-09-27
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Replacement of memory spare location, portion, or segment
C714S723000, C365S185090
Reexamination Certificate
active
06950971
ABSTRACT:
A memory apparatus is configured by obtaining test information for each of group of memory locations within the memory apparatus, compressing the test information to produced compressed test information and, based on the compressed test information, replacing a group of redundant memory circuits respectively associated with the group of memory locations.
REFERENCES:
patent: 5418452 (1995-05-01), Pyle
patent: 6163863 (2000-12-01), Schicht
patent: 6311299 (2001-10-01), Bunker
patent: 6374378 (2002-04-01), Takano et al.
patent: 6484278 (2002-11-01), Merritt et al.
patent: 6543015 (2003-04-01), Wang et al.
patent: 6564346 (2003-05-01), Vollrath et al.
Boehler Thomas
Lehmann Gunther
Brinks Hofer Gilson & Lione
Britt Cynthia
De'cady Albert
Infineon - Technologies AG
LandOfFree
Using data compression for faster testing of embedded memory does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Using data compression for faster testing of embedded memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Using data compression for faster testing of embedded memory will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3417999