Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1999-12-30
2002-12-24
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
Reexamination Certificate
active
06499120
ABSTRACT:
BACKGROUND
1. Technical Field
This disclosure relates to semiconductor testing and more particularly, to a method for providing failure bit maps from redundancy data for semiconductor devices.
2. Description of the Related Art
Semiconductor devices, especially memory devices, are typically tested by generating a pattern of inputs and transferring the pattern of inputs to the array of memory cells. The data written to the memory cells is then retrieved and compared to the input pattern to identify abnormalities or failures. The failures of the cells are stored in a tester in an address failure memory and correlated to repair the failures by replacing failed cells with redundancies. Typically, a tester provides a failure redundancy latch map (FRL) with 256 regions associated with the amount of input/output ports (I/O's) regardless of the size of the device. This results in further limitations on the map's capabilities for displaying a bit map.
In typical set ups, a complete test sequence is run on the tester to identify failures, which are stored in an address fail memory, and perform redundancy calculations. Then, to provide a bit map of the failures, the data in the address fail memory is dumped to a file to recollect the test data for the bit map. In some cases the entire chip or wafer must be retested to retrieve the data. This dumping process may be very time consuming, and increases test time. Further, to reduce time specialized software programs are needed to reduce this dumping time. These specialized programs tend to be very expensive.
Therefore, a need exists for a method of providing a bit map which utilizes redundancy data in a first test run to generate a bit map display while eliminating the time needed for additional data transfers.
SUMMARY OF THE INVENTION
A method for displaying failure information for semiconductor devices, in accordance with the present invention, includes testing a semiconductor device with a tester to determine failures, performing a redundancy calculation to repair the failures, storing results of the redundancy calculation in a file which identifies only addresses of components which have failed, converting the file to a display format and displaying the display format to provide a bit fail map for the semiconductor device such that sparse failures are displayed in addition to row and column failures without employing the tester to regenerate fail data.
In alternate methods, the step of adjusting a resolution of the bit fail map by programming a repair control file may be included. The resolution may be adjusted to display single cell failures. The file provided by the redundancy calculation may include binary data. The step of converting the file to a display format may include the step of employing an automatic pattern recognition program (APRC) to translate the file. The method may further include the step of analyzing the display to identify locations of failures. The steps of storing results of the redundancy calculation and displaying the display format are preferably performed during a single test run of a production test. This provides the bit map data without having to regenerate the data. The step of displaying the display format may include displaying column failures, row failures and spares failures on a same map. The step of converting the file to a display format may include manually assigning reference addresses to provide a method for displaying the data. The above methods may be implemented by a program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for displaying failure information after testing a semiconductor device for failures.
Another method for displaying failure information for a semiconductor memory device includes the steps of testing a semiconductor memory device to determine failures in a memory array of the device, performing a plurality of tests, each test followed by a redundancy calculation to repair the failures of the test, storing results of each redundancy calculation in a binary file which identifies component failure due to the tests, wherein the redundancy calculation results include row addresses, column address and sparse failure addresses, converting the binary file to a display format using an automatic pattern recognition program (APRC) and displaying the display format on a monitor to provide a bit fail map for the semiconductor device.
In other methods, the step of analyzing the display may be included. The steps of storing results of the redundancy calculation and displaying the display format to provide a bit fail map for the semiconductor device may be performed during a single test run of a production test. The step of displaying the display format to provide a bit fail map for the semiconductor device may include displaying column failures, row failures and sparse bit failures on a same map. The step of adjusting a resolution of the bit fail map by programming a repair control file may be included. The resolution may be adjusted to display single cell failures.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
REFERENCES:
patent: 5720031 (1998-02-01), Lindsay
patent: 5917764 (1999-06-01), Ohsawa et al.
Tanoi, BIST: Required for Embedded DRAM, IEEE, p. 1149, 1998.*
Tanoi et al., On-Wafer BIST of a 200Gb/s Failed-Bit Search for 1Gb DRAM, IEEE, p. 70-73, 1997.
Braden Stanton
Chase Shelly A
De'cady Albert
Infineon Technologies Richmond LP
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