Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-06-20
2006-06-20
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S755000, C375S262000, C375S341000
Reexamination Certificate
active
07065699
ABSTRACT:
Operands (90) that are represented in two's complement format are prepared for use in binary arithmetic. For each operand, it is determined (91, 93) whether an original value thereof is within a predetermined proximity of a maximum positive/maximum negative value boundary associated with the two's complement format. If any of the original operand values is within the predetermined proximity, all of the original operand values are adjusted (95) to produce respectively corresponding adjusted operand values (96) for use in a binary arithmetic operation.
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C. Bernard Shung, Paul H. Siegel, Gottfried Ungerboeck, and Hemant K. Thapar, “VLSI Architectures for Metric normalization in Viterbi Algorithm,”IEEE ICC, pp. 1723-1728, 1990.
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Gatherer Alan
Wolf Tod David
Abraham Esaw
Brady III W. James
De'cady Albert
Stewart Alan K.
Telecky , Jr. Frederick J.
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