Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2008-09-09
2008-09-09
Louis-Jacques, Jacques (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C716S030000, C716S030000, C716S030000, C716S030000, C703S023000, C703S025000
Reexamination Certificate
active
10956990
ABSTRACT:
Methods and structures utilizing multiple configuration bitstreams to program integrated circuits (ICs) such as programmable logic devices, thereby enabling the utilization of partially defective ICs. A user design is implemented two or more times, preferably utilizing different programmable resources as much as possible in each configuration bitstream. The resulting user configuration bitstreams are stored along with associated test bitstreams in a memory device, e.g., a programmable read-only memory (PROM). Under the control of a configuration control circuit or device, the test bitstreams are loaded into a partially defective IC and tested using an automated testing procedure. When a test bitstream is found that enables the associated user design to function correctly in the programmed IC, i.e., that avoids the defective programmable resources in the IC, the associated user bitstream is loaded into the IC, the configuration procedure terminates, and the programmed IC begins to function according to the user design.
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Cartier Lois D.
Louis-Jacques Jacques
Maunu LeRoy D.
Merant Guerrier
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