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Memory circuit and method for reading out data

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Memory circuit being capable of compression test

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Memory circuit having a controllable output drive

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Memory circuit having a controllable output drive

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Memory circuit having parity cell array

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Memory circuit scan arrangement

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Memory circuit testing system, semiconductor device, and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Memory control circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Memory controller with a self-test function, and method of...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Memory data path circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Memory data verify operation

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Memory device and input signal control method of a memory...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Memory device and method for redundancy/self-repair

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Memory device capable of detecting its failure

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Memory device test system and method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Memory device testing apparatus and data selection circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Memory device testing system and method having real time...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Memory device with comparison units to check functionality...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Memory devices operable in both a normal and a test mode and met

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Memory devices with selectively enabled output circuits for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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