Memory device testing system and method having real time...

Details Memory device testing system and method having real time... Memory device testing system and method having real time...

2006-04-05

2008-11-18

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

Reexamination Certificate

active

07454671

ABSTRACT:
A memory device test system includes a signal generator providing memory command, address and write data signal to write data in a memory device and then read the data from the memory device. Each item of read data is compared to the corresponding item of write data, and fail data is produced indicative of the results of the comparison. The fail data is applied to a real time repair analyzer, which also receives an address of the read data being read to generate each item of fail data. The addresses are captured responsive to respective fail data signals to provide a record of the block, column and bit of each word of data read from a defective memory cell. The addresses are accumulated while the data are read from the memory device during testing so that a repair solution is available virtually as soon as the test has been completed.

REFERENCES:
patent: 6026505 (2000-02-01), Hedberg et al.
patent: 6397349 (2002-05-01), Higgins et al.
patent: 7228468 (2007-06-01), Wu et al.
patent: 2002/0019957 (2002-02-01), Higgins et al.

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