Memory circuit and method for reading out data

Details Memory circuit and method for reading out data Memory circuit and method for reading out data

2006-07-18

2006-07-18

Ton, David (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S721000

Reexamination Certificate

active

07080297

ABSTRACT:
It is possible to read out data in accordance with a read-out address from memory cells via bit lines and primary sense amplifiers. Each secondary sense amplifier is assigned a group of primary sense amplifiers. It is possible for the primary sense amplifiers of a group to be connected to one of the secondary sense amplifiers in each case via switching devices in order to apply the datum from one of the primary sense amplifiers to the assigned secondary sense amplifier via the switching device selected by the read-out address. For reading out data, a test control unit is provided to connect some of the switching devices in parallel depending on a test mode signal and depending on a read-out address, so that in each case one of the group of primary sense amplifiers is connected to the assigned secondary sense amplifiers.

REFERENCES:
patent: 5901105 (1999-05-01), Ong et al.
patent: 5936975 (1999-08-01), Okamura
patent: 6470465 (2002-10-01), Shim et al.
patent: 6542973 (2003-04-01), Hsu et al.
patent: 6876557 (2005-04-01), Hsu et al.
patent: 6961273 (2005-11-01), Boldt et al.

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