Memory circuit scan arrangement

Details Memory circuit scan arrangement Memory circuit scan arrangement

2006-11-07

2006-11-07

Kerveros, James C. (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

Reexamination Certificate

active

07134058

ABSTRACT:
A semiconductor integrated circuit comprises a plurality of combinational logic components, a memory and a testing arrangement for configuring the memory prior to testing the combinational logic components using one or more scan chains. The arrangement includes a bit pattern generator for generating a predetermined bit pattern for writing to the memory, a switching arrangement for selectively switching the memory input to receive data from the combinational logic components or from the data generator. The switching arrangement and data generator are arranged to input the predetermined bit pattern to the memory prior to testing the integrated circuit.

REFERENCES:
patent: 4481627 (1984-11-01), Beauchesne et al.
patent: 5557619 (1996-09-01), Rapoport
patent: 6094736 (2000-07-01), Komoike
patent: 6148426 (2000-11-01), Kim et al.
patent: 6263461 (2001-07-01), Ayres et al.

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