Memory circuit testing system, semiconductor device, and...

Details Memory circuit testing system, semiconductor device, and... Memory circuit testing system, semiconductor device, and...

2003-06-06

2009-08-18

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C365S201000

Reexamination Certificate

active

07577884

ABSTRACT:
A semiconductor device that performs refresh tests of a plurality of individual memories built into the same chip and prevents excessive testing during the refresh test. When a first testing circuit enters a wait state, the first testing circuit issues a refresh command REF to a first memory circuit. Then, the first memory circuit refreshes the memory cells until a second testing circuit enters the wait state. That is, since the memory cells of the first memory circuit are refreshed until the writing to a second memory circuit ends, the refresh test time of the first and second memory circuits are the same.

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patent: 6141765 (2000-10-01), Sherman
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patent: 6453434 (2002-09-01), Delp et al.
patent: 11-086598 (1999-03-01), None
patent: 2000-163997 (2000-06-01), None
“Quality memory blocks-balancing the trade-offs” by Prince, B. IEEE First International Symposium on Quality Electronic Design, 2000. ISQED 2000. Proceedings Publication Date: 2000 on pp. 109-114 Meeting Date: Mar. 20, 2000-Mar. 22, 2000 ISBN: 0-7695-0525-2 INSPEC Accession No. 6622773.

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