Memory devices with selectively enabled output circuits for...

Details Memory devices with selectively enabled output circuits for... Memory devices with selectively enabled output circuits for...

2007-01-23

2007-01-23

Decady, Albert (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C365S201000, C714S030000, C714S724000

Reexamination Certificate

active

10648086

ABSTRACT:
A memory device, such as a DDR SDRAM, may be provided in which subsets of data output circuits of the device can be selectively enabled to allow sets of data output pins to be connected in common in a testing configuration. In some embodiments, a memory device includes a plurality of data output circuits, respective ones of which are configured to receive data from respective internal data lines and respective ones of which are coupled to respective data input/output pins. The device further includes a data output control circuit operative to selectively enable subsets of the plurality of data output circuits to drive their respective corresponding data input/output pins responsive to an externally-applied control signal. The data output control circuit may be operative to selectively cause subsets of the plurality of data output circuits to present a high impedance at their respective corresponding data input/output pins. The invention may be embodied as devices and methods.

REFERENCES:
patent: 4495603 (1985-01-01), Varshney
patent: 5293386 (1994-03-01), Muhmenthaler et al.
patent: 5910923 (1999-06-01), Brown et al.
patent: 2003/0110428 (2003-06-01), Ochoa et al.

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