Memory circuit having parity cell array

Details Memory circuit having parity cell array Memory circuit having parity cell array

2006-04-18

2006-04-18

Lamarre, Guy (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S800000, C365S200000, C365S201000, C365S222000

Reexamination Certificate

active

07032142

ABSTRACT:
A memory circuit has: a real cell array; a parity generating circuit for generating a parity bit from data of the real cell array; a parity cell array; a refresh control circuit, which sequentially refreshes the real cell array, and when an internal refresh request and a read request coincide, prioritizes a refresh operation; a data recovery section, which, in accordance with the parity bit read out from the parity cell array, recovers data read out from the real cell array; and an output circuit for outputting data from the real cell array. Further, the memory circuit has a test control circuit, which, at a first test mode, prohibits a refresh operation for the real cell array to output data read out from the real cell array, and, at a second test mode, controls the output circuit so as to output data read out from the parity cell array.

REFERENCES:
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patent: 4794597 (1988-12-01), Ooba et al.
patent: 6185718 (2001-02-01), Dell et al.
patent: 6233717 (2001-05-01), Choi
patent: 2004/0221143 (2004-11-01), Wise et al.
patent: 81/03567 (1981-12-01), None
U.S. Appl. No. 10/001,790, filed Dec. 5, 2001.

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