Memory device test system and method

Details Memory device test system and method Memory device test system and method

2005-04-12

2005-04-12

Chung, Phung My (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C702S124000

Reexamination Certificate

active

06880117

ABSTRACT:
A testing system is described for testing a memory device. The testing system includes a timing generator, an optional frequency multiplier circuit, a pattern generator, and a waveform shaping circuit. The timing generator generates a first clock signal. The frequency multiplier circuit receives the first clock signal, and uses the first clock signal to produce a second clock signal. In general, the second clock signal has a frequency greater than a frequency of the first clock signal. The frequency of the second clock signal may twice the frequency of the first clock signal. The testing system provides the second clock signal to the memory device such that operations within the memory device are synchronized to the second clock signal. The waveform shaping circuit produces an address signal synchronized to the first clock signal, and provides the address signal to the memory device when reading data from the memory device. In another embodiment, the first clock signal is not used and the address signals are synchronized to every two cycles of the second clock signal. A method for testing a memory device, which may be embodied in the testing system, is also described.

REFERENCES:
patent: 5587950 (1996-12-01), Sawada et al.
patent: 6173238 (2001-01-01), Fujisaki
patent: 6243422 (2001-06-01), Urabe et al.
patent: 6361501 (2002-03-01), Amano et al.
patent: 6543015 (2003-04-01), Wang et al.

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