Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2007-05-15
2007-05-15
Lamarre, Guy (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S103000
Reexamination Certificate
active
10024646
ABSTRACT:
The preferred embodiments described herein provide a memory device and method for redundancy/self-repair. In one preferred embodiment, a memory device is provided comprising a primary block of memory cells and a redundant block of memory cells. In response to an error in writing to the primary block, a flag is stored in a set of memory cells allocated to the primary block, and the redundant block is written into. In another preferred embodiment, an error in writing to a primary block is detected while an attempt is made to write to that block. In response to the error, the redundant block is written into. In yet another preferred embodiment, a memory device is provided comprising a three-dimensional memory array and redundancy circuitry. In still another preferred embodiment, a method for testing a memory array is provided. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another.
REFERENCES:
patent: 4646266 (1987-02-01), Ovshinsky et al.
patent: 5278839 (1994-01-01), Matsumoto et al.
patent: 5313425 (1994-05-01), Lee et al.
patent: 5432729 (1995-07-01), Carson et al.
patent: 5469450 (1995-11-01), Cho et al.
patent: 5579265 (1996-11-01), Devin
patent: 5642318 (1997-06-01), Knaack et al.
patent: 5701267 (1997-12-01), Masuda et al.
patent: 5708667 (1998-01-01), Hayashi
patent: 5748545 (1998-05-01), Lee et al.
patent: 5751647 (1998-05-01), O'Toole
patent: 5757700 (1998-05-01), Kobayashi
patent: 5784391 (1998-07-01), Konigsburg
patent: 5796694 (1998-08-01), Shirane
patent: 5831989 (1998-11-01), Fujisaki
patent: 5835396 (1998-11-01), Zhang
patent: 5835509 (1998-11-01), Sako et al.
patent: 5872790 (1999-02-01), Dixon
patent: 5909049 (1999-06-01), McCollum
patent: 5920502 (1999-07-01), Noda et al.
patent: 5943254 (1999-08-01), Bakeman, Jr. et al.
patent: 5986950 (1999-11-01), Joseph
patent: 6016269 (2000-01-01), Peterson et al.
patent: 6026476 (2000-02-01), Rosen
patent: 6034882 (2000-03-01), Johnson et al.
patent: 6185122 (2001-02-01), Johnson et al.
patent: 6205564 (2001-03-01), Kim et al.
patent: 6216247 (2001-04-01), Creta et al.
patent: 6236587 (2001-05-01), Gudesen et al.
patent: 6344755 (2002-02-01), Reddy et al.
patent: 6420215 (2002-07-01), Knall et al.
patent: 6438044 (2002-08-01), Fukuda
patent: 6446242 (2002-09-01), Lien et al.
patent: 6462988 (2002-10-01), Harari
patent: 6498749 (2002-12-01), Cuppens et al.
patent: 6515923 (2003-02-01), Cleeves
patent: 6525953 (2003-02-01), Johnson
patent: 6545501 (2003-04-01), Bailis et al.
patent: 6553510 (2003-04-01), Pekny
patent: 6567287 (2003-05-01), Scheuerlein
patent: 6597595 (2003-07-01), Ichiriu et al.
patent: 6658438 (2003-12-01), Moore et al.
patent: 6661730 (2003-12-01), Scheuerlein et al.
patent: 6728149 (2004-04-01), Akamatsu
patent: 2002/0028541 (2002-03-01), Lee et al.
patent: 2002/0085431 (2002-07-01), Jeon et al.
patent: 2002/0162062 (2002-10-01), Hughed et al.
patent: 2003/0021176 (2003-01-01), Hogan
patent: 2003/0115514 (2003-06-01), Ilkbahar et al.
patent: 2003/0115518 (2003-06-01), Kleveland et al.
patent: 2004/0255089 (2004-12-01), Unno
patent: 2 265 031 (1993-09-01), None
patent: WO99/14763 (1997-09-01), None
patent: WO 99/14763 (1999-03-01), None
“Computer Engineering: Hardware Design,” M. Morris Mano, Chapter 6-4 Error Detection and Correction, pp. 199-202 (1988).
“Reed-Solomon Codes,” http://www.4i2i.com/reed—solomon—codes.htm, 8 pages (1998).
“A 30 ns 64Mb DRAM with Built-in Self-Test and Repair Function,” 1992 IEEE International Solid State Circuits Conference, Digest of Technical Papers, pp. 150-151 (Feb. 1992).
“64M×8 Bit NAND Flash Memory,” Samsung Electronics, 40 pages (Oct. 27, 2000).
“Exotic Memories, Diverse Approaches,” EDN Asia, pp. 22-33 (Sep. 2001).
“A Vertical Leap for Microchips,” Thomas H. Lee, Scientific American, 8 pages (Jan. 2002; printed Dec. 10, 2001).
“Three-Dimensional Memory Array and Method of Fabrication,” U.S. Appl. No. 09/560,626, filed Apr. 28, 2000; inventor: Johan Knall.
“Memory Devices and Methods for Use Therewith,” U.S. Appl. No. 09/748,589, filed Dec. 22, 2000; inventors: Roger W. March, Christopher S. Moore, Daniel Brown, Thomas H. Lee, and Mark G. Johnson.
“Three-Dimensional Memory Array and Method for Storing Data Bits and ECC Bits Therein,” U.S. Appl. No. 09/747,574, filed Dec. 22, 2000; inventors: Thomas H. Lee, James M. Cleeves, and Mark G. Johnson.
“Memory Device and Method for Sensing while Programming a Non-Volatile Memory Cell,” U.S. Appl. No. 09/896,815, filed Jun. 29, 2001; inventors: Bendik Kleveland, James M. Cleeves, and Roy E. Scheuerlein.
“A 16Mb Mask ROM with Programmable Redundancy,” Nsruka et al., ISSCC 1989/Session 10: Nonvolatile Memories/Paper THAM 10.1, 2 pages, Feb. 16, 1989.
“Circuit Technologies for 16Mb DRAMs,” Mano et al., ISSCC 1987/Session I: MEGABIT DRAMs/Paper WAM 1.6, 2 pages, Feb. 27, 1987.
“Memory Device and Method for Storing and Reading Data in a Write-Once Memory Array,” U.S. Appl. No. 09/877,720, filed Jun. 8, 2001; inventors: Christopher S. Moore, James E. Schneider, J. James Tringali and Roger W. March.
“Memory Device and Method for Storing and Reading a File System Structure in a Write-Once Memory Array,” U.S. Appl. No. 09/877,719, filed Jun. 8, 2001; inventors: Christopher S. Moore, James E. Schneider, J. James Tringali and Roger W. March.
“Method for Reading Data in a Write-Once Memory Device Using a Write-Many File System,” U.S. Appl. No. 09/818,138, filed Jun. 8, 2001; inventors: J. James Tringali, Christopher S. Moore, Roger W. March, James E. Schneider, Derek Bosch, and Daniel C. Steere.
“Method for Re-Directing Data Traffic in a Write-Once Memory Device,” U.S. Appl. No. 09/877,691, filed Jun. 8, 2001; inventors: J. James Tringali, Christopher S. Moore, Roger W. March, James E. Schneider, Derek Bosch, and Daniel C. Steere.
“Method for making a Write-Once Memory Device Read Compatible with a Write-Many File System,” U.S. Appl. No. 10/023,468, filed Dec. 14, 2001; inventors: Christopher S. Moore, Matt Fruin, Colm Lysaght, and Roy E. Scheuerlein.
Search History for U.S. Appl. No. 10/402,385, 3 pages, Nov. 17, 2004.
Ilkbahar Alper
Kleveland Bendik
Scheuerlein Roy E.
Brinks Hofer Gilson & Lione
Lamarre Guy
SanDisk 3D LLC
Tabone, Jr. John J.
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