Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2007-08-23
2009-10-13
Trimmings, John P (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S025000, C714S030000, C714S042000, C714S048000, C714S703000, C714S709000, C714S715000, C714S719000, C714S720000, C714S733000, C714S735000, C714S798000, C714S799000, C714S818000, C714S819000, C714S824000, C365S201000
Reexamination Certificate
active
07603596
ABSTRACT:
A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for receiving and storing therein the data which have passed through the data input section; memory cell arrays for storing therein the data which have passed through the data input section; and a data compressor for determining whether or not the data stored in the latch section and the data stored in the memory cell arrays are identical to each other.
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Cha Jae Hoon
Lee Geun Il
Hynix / Semiconductor Inc.
Ladas & Parry LLP
Trimmings John P
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