Memory device testing apparatus and data selection circuit

Details Memory device testing apparatus and data selection circuit Memory device testing apparatus and data selection circuit

1999-05-12

2002-12-03

Moise, Emmanuel L. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S719000, C714S720000

Reexamination Certificate

active

06490700

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a memory device testing apparatus. In particular, the present invention relates to a memory device testing apparatus for testing a packet system memory device.
2. Description of Related Art
FIG. 1
shows a schematic view of a conventional memory device testing apparatus for testing a memory device. This memory device testing apparatus has a pattern generator
10
, a pin data selector
20
, a waveform shaper
30
, a memory device socket
40
, and a comparator
50
. A memory device
45
is held into a socket
42
on the memory device socket
40
during the test. The pattern generator
10
generates a pattern signal
12
, which contains an address, a control signal
25
, and data to be provided to the memory device
45
. The data contains an expectation value data signal
27
, which is compared with output a signal
44
output from the memory device
45
by the comparator
50
. The pattern signal
12
generated from the pattern generator
10
is sent to the pin data selector
20
.
A test data signal
26
is to be written into the memory device
45
according to the address and the control signal
25
provided to the memory device
45
. The expectation value data signal
27
is the expectation value which is expected to output from memory device
45
if the memory device
45
is normal. The expectation value data signal
27
is compared with the output signal
44
read from the memory device socket
40
by comparator
50
.
The pin data selector
20
selects the address and the control signal
25
, which is part of the pattern signal
12
, to allocate the address and the control signal
25
to corresponding pins on the memory device socket
40
. The Pin data selector
20
outputs the test data signal
26
, which is written into the memory device
45
, and the expectation value data signal
27
, which is compared with the output signal
44
output from the memory device
45
, by the comparator
50
. The test data signal
26
and the expectation value data signal
27
have the same signal pattern.
The address and the control signal
25
generated from the pin data selector
20
are sent to the waveform shaper
30
. The waveform shaper
30
shapes the waveform of the address and the control signal
25
to adjust the waveform of the address and the control signal
25
to the characteristic of the memory device
45
, and the waveform shaper
30
outputs the waveform-shaped address and control signal
32
. The waveform shaper
30
also adjusts the timing for providing the signal to the memory device
45
. The waveform-shaped address and control signal
32
are provided to the memory device socket
40
.
When the control signal
25
means write request, which requests the data to be written, the waveform of the test data signal
26
is shaped by the waveform shaper
30
, and the resulting waveform-shaped test data signal
33
is written into the memory device
45
. The test data, which is written into the memory device
45
, is output from the memory device socket
40
in response to a read request signal generated from the pattern generator
10
. The output signal
44
is input to the comparator
50
to be compared with the expectation value data signal
27
.
FIG. 2
shows a block diagram of a sub pin data selector
20
a
in the pin data selector
20
. The pin data selector
20
has the same number of sub pin data selectors
20
a
as the number of signal input pins of the memory device
45
. The sub pin data selector
20
a
has multiplexers
21
a
and
23
a
and registers
22
a
and
24
a
. The registers
22
a
and
24
a
are respectively connected to the control inputs of the multiplexers
21
a
and
23
a.
The pattern signal
12
generated from the pattern generator
10
is input to the multiplexer
21
a
. The multiplexer
21
a
is controlled by the register
22
a
. The register
22
a
indicates which signal should be selected from the pattern signal
12
to the multiplexer
21
a
. Then, the multiplexer
21
a
selects one of the addresses signals and one of the control signals
25
a
to be provided to a specific pin of the memory device
45
.
Here, multiplexer
23
a
and register
24
a
are not used. Each of the addresses and control signals
25
a
selected from each sub pin data selector
20
a
is sent to the waveform shaper
30
. The selected addresses and control signals
25
a
generate one combined address and control signal
25
as a whole. Address and control signal
25
is sent through the waveform shaper
30
to the memory device socket
40
to the memory device
45
.
The test data
26
and the expectation value data signal
27
are also output from the sub pin data selector
20
a.
When the test data
26
is supplied to the sub pin data selector
20
a
, the register
22
a
indicates which test data signal should be selected from the pattern signal
12
to the multiplexer
21
a
. Then, the multiplexer
21
a
selects a test data signal
26
a
from the pattern signal
12
. The waveform of the test data signal
26
a
is shaped by the waveform shaper
30
, and the resulting waveform-shaped test data signal
33
a
is written into the memory device
45
.
The pattern generator
10
provides a read signal to the memory device
45
, and the memory device
45
outputs written test data as the output signal
44
to the comparator
50
. At that time, the pin data selector
20
outputs the expectation value data signal
27
to the comparator
50
. The sub pin data selector
20
a
selects the expectation value data signal
27
a
by using the multiplexer
23
a
and the register
24
a
in the same way as when the sub pin data selector
20
a
selects the test data signal
26
a
. The comparator
50
compares the output signal
44
with the expectation value data signal
27
.
As the technology of memory devices has developed, the packet system memory device has come into use, and it is difficult to test packet system memory devices with the conventional memory test apparatus. A packet system memory device is a memory which inputs a plurality of command signals in a packet and writes data sequentially to sequential addresses at high speed. It is important to discover how to generate a test data pattern for testing packet system memory devices.
FIG. 3
shows the pin components of a packet system memory device. This packet system memory device has 10 input pins CA
0
-CA
9
to input address signals and control signals, a clock pin CLK, and
18
data input and output pins DQ
0
-DQ
17
. These data input and output pins are divided into 2 sets, DQ
0
-DQ
8
and DQ
9
-DQ
17
, and each set inputs and outputs 8 bits of data and 1 parity bit.
FIG. 4
shows an example of a read-write request packet, which is the command signal to be input to the packet system memory device. In this example, a command codes, Cmd
5
-Cmd
0
, bank addresses, BNK
2
-BNK
0
, row addresses, Row
9
-Row
0
, and column addresses, Col
6
-Col
0
, are input to the memory device from 10 pins CA
0
-CA
9
over 4 cycles of the clock CLK.
FIG. 5
shows the allocation of tester resources, which corresponds to the read-write request packet shown in FIG.
4
. As shown in
FIG. 5
, multiple signals are allocated to a single pin to input the command signal to the packet system memory device. In this example, 4 signals, C
5
, X
8
,
0
, and Y
0
are allocated to pin CA
0
. However, the pin data selector
20
of the conventional memory test device can allocate only one signal to a pin. And, the packet signals for each cycle must be generated from the pattern generator
10
to test the packet system memory device with the conventional memory test apparatus.
But it is difficult to generate a packet of signals, which is a block of sequential signals comprising address signals and control signals, by dividing the packet of signals one cycle by one cycle. Especially, as the capacity of memory device become larger, it becomes more difficult to generate the data pattern. In this case, the cost of generating the data pattern increases, so that with the cost of testing memory d

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