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High-speed serial transfer device test data storage medium...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate

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High-speed test system for a memory device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent

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Hub for testing memory and methods thereof

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate

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Hub, memory module, memory system and methods for reading...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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I/O compression circuit for a semiconductor memory device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate

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IC test system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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In-service raid mirror reconfiguring

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate

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Increasing possible test patterns which can be used with...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Information processing apparatus and nonvolatile...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Input/output compression test circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Integrated circuit and method for testing it

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Integrated circuit and method for testing memory on the...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate

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Integrated circuit devices with mode-selective external...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Integrated circuit having memory built-in self test (BIST) for d

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent

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Integrated circuit implementing internally generated commands

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate

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Integrated circuit in a maximum input/output configuration

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Integrated circuit internal signal monitoring apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate

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Integrated circuit memory devices and methods for generating...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Integrated circuit memory devices including internal stress...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Integrated circuit test mode with externally forced reference vo

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent

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