Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1999-05-20
2002-07-16
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
Reexamination Certificate
active
06421797
ABSTRACT:
RELATED APPLICATION
This application claims the benefit of Korean Patent Application No. 98-19585, filed May 28, 1998, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates to the field of integrated circuit memories, and, more particularly, to test circuits that can reduce the time needed to test an integrated circuit memory.
BACKGROUND OF THE INVENTION
Integrated circuit memory devices are routinely tested by writing a test pattern of bits into particular memory locations and then reading the test pattern out to verify that the test pattern written into the memory and the test pattern read out of the memory are consistent. To improve the efficiency of the testing operation, many memory devices have a parallel bit test mode in which a plurality of bits are tested simultaneously, thereby shortening the test time at both a wafer level and a package level. More specifically, N-bits of data are read in a parallel bit test to determine if the data are consistent with the data previously written into the same storage cells. Typically, the test will generate a logic “1” or “0” corresponding to a “matched” or “unmatched” result, respectively. Those memory locations that produce an unmatched result can be repaired through the use of well known redundancy schemes.
Parallel bit testing can significantly reduce testing time even in integrated circuit memories in which the column width is a single bit (e.g., memories with a x1 bit architecture). The number of testing cycles needed to test a semiconductor memory device one bit at time can be reduced by a factor of 1/N if parallel bit testing is used. Moreover, for memory devices that have several input/output (I/O) lines for testing multiple bits in parallel, the testing efficiency can nevertheless be further improved by using each I/O line to report parallel bit test results.
As the degree of integration of memory devices is increased, however, the number of bits to be simultaneously tested in a parallel bit test also needs to increase to minimize any increase in test time. For example, a 16-bit parallel bit test is typically used in 16M dynamic random access memories (DRAMs) while a 32-bit parallel bit test is typically used 64M DRAMs.
Unfortunately, because device integration is increasing at a more rapid rate than parallel bit test width is increasing, the additional time spent in testing will typically translate into increased manufacturing costs as conventional parallel bit testing fails to keep up with more highly integrated memory devices. Consequently, there exists a need for an improved parallel bit testing system that further reduces the time needed to test an integrated circuit memory device and thereby reduces testing costs.
SUMMARY OF THE INVENTION
Certain objects, advantages, and features of the invention will be set forth in the description that follows and will become apparent to those skilled in the art upon examination of the following or may be learned with the practice of the invention.
It is an object of the present invention to provide improved integrated circuit memory devices that can perform a parallel bit test on a memory cell array.
It is a further object of the present invention to allow multiple parallel bit test results to be transferred to an output during a time interval that is equivalent to a single clock cycle period.
To achieve the advantages and features, the present invention is generally directed to integrated circuit memory devices and methods that can generate and output multiple parallel bit test results during a time interval equal to a period of a single clock cycle. More specifically, the integrated circuit memory devices include a memory cell array and a parallel bit test circuit that is responsive to a first clock signal and is used to test the memory cell array. The parallel bit test circuit receives a plurality of data sets from the memory cell array and generates a test result for each data set. These test results are output during non-overlapping portions of a time interval that has a duration equivalent to the first clock signal period. Accordingly, the output of one test result does not interfere with the output of another test result.
In an illustrative embodiment of the invention, the parallel bit test circuit includes a pair of comparison circuits and a pair of latch circuits. In addition, the integrated circuit memory devices further include a clock generator that produces a pair of complementary clock signals (i.e., second and third clock signals) in response to the first clock signal. The second clock signal is responsive to a rising edge of the first clock signal while the third clock signal is responsive to a falling edge of the first clock signal. Test results held in the latch circuits are output to the exterior through first and second output buffers where the first output buffer is responsive to the second clock signal while the second output buffer is responsive to the third clock signal. As a result, multiple test results can be transferred to the exterior during a time interval equivalent to the duration of a single cycle of the first clock signal.
The invention can also be viewed as providing a method for performing a parallel bit test on an integrated circuit memory device wherein multiple parallel bit test results are generated and output during a time interval equal to a period of a single clock cycle. In this regard, the method can be broadly summarized by the following steps: A plurality of data sets from a memory cell array are tested and a test result is generated for each data set. These test results are transferred to an output of the integrated circuit memory device in response to a first clock signal. In particular, each test result is transferred during non-overlapping portions of a time interval that has a duration equivalent to the first clock signal period. Accordingly, the output of one test result does not interfere with the output of another test result.
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patent: 5214655 (1993-05-01), Eichelberger et al.
patent: 5301142 (1994-04-01), Suzuki et al.
patent: 5996097 (1999-11-01), Evans et al.
patent: 6064601 (2000-06-01), Yoo et al.
patent: 2235555 (1991-03-01), None
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Chung Phung M.
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
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