Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2010-11-05
2011-12-27
Chung, Phung M (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S738000
Reexamination Certificate
active
08086918
ABSTRACT:
A test pattern generating unit generates a test pattern in which unconverted data is arranged such that same values of 0 or 1 bits in converted data according to a code conversion table are successively transferred to each of a plurality of serial transfer channels that a high-speed serial transfer device has. A basic pattern setting unit sets a basic pattern while considering a byte order method and an RD value of code conversion in the high-speed serial transfer device. A basic pattern resetting unit resets the basic pattern in accordance with a channel usage method of a bit transfer order in the high-speed serial transfer device. A basic pattern rearranging unit performs rearrangement such that the basic pattern is transferred to each of the channels in accordance with the number of used channels and a channel usage method such as bit transfer order in the high-speed serial transfer device.
REFERENCES:
patent: 4369511 (1983-01-01), Kimura et al.
patent: 4788684 (1988-11-01), Kawaguchi et al.
patent: 5970073 (1999-10-01), Masuda et al.
patent: 6094737 (2000-07-01), Fukasawa
patent: 6680970 (2004-01-01), Mejia
patent: 7333518 (2008-02-01), Sakai et al.
patent: 2002/0018492 (2002-02-01), Sakai et al.
patent: 2004/0042544 (2004-03-01), Mejia
patent: 02-162823 (1990-06-01), None
patent: 10-243017 (1998-09-01), None
patent: 2003-330918 (2000-11-01), None
patent: 2000-353236 (2000-12-01), None
patent: 2001-197043 (2001-07-01), None
patent: 2002-051033 (2002-02-01), None
patent: 2002-084247 (2002-03-01), None
patent: 2002-527832 (2002-08-01), None
patent: 00/22565 (2000-04-01), None
U.S. Appl. No. 11/398,615, filed Apr. 6, 2006, Tetsuo Kurayama, Fujitsu Limited.
“What is a pseudorandom number sequence?”, URL: http://infohost.nmt.edu/tcc/help/lang/fortran/pseudo.html, Dec. 1995.
Japanese Patent Office Action mailed Apr. 3, 2007 in Japanese Application No. 2006-527215.
Notice of Allowance mailed Aug. 6, 2010 in U.S. Appl. No. 11/398,615.
Office Action mailed Apr. 1, 2010 in U.S. Appl. No. 11/398,615.
Office Action mailed Mar. 5, 2009 in U.S. Appl. No. 11/398,615.
Japanese Office Action mailed Jan. 25, 2011 in corresponding Japanese Application No. 2005-361340.
Japanese Office Action issued Jan. 25, 2011 in corresponding Japanese Patent Application 2006-001574.
Chung Phung M
Fujitsu Limited
Staas & Halsey , LLP
LandOfFree
High-speed serial transfer device test data storage medium... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High-speed serial transfer device test data storage medium..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High-speed serial transfer device test data storage medium... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4298795