Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent
1999-05-27
2000-11-28
De Cady, Albert
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
365201, G11C 2900
Patent
active
06154860&
ABSTRACT:
A memory device requires a minimum of two input/output lines from an external testing device to be coupled thereto. A first DQ line from the memory device provides a direct data path from the array so that the external tester can read data from the array at the maximum speed of the memory device. Test mode circuitry for multiplexing and comparing multiple DQ lines during address compression mode is coupled to two or more DQ lines, including the first DQ line. The compression mode testing circuitry can include on-chip comparators that compare the data simultaneously written to, and read from, the memory device. The comparison circuitry outputs a data test flag indicating whether or not the data read from the memory device matches. The test flag is output through a multiplexer to a second DQ line. As a result, the speed of the device can be tested from the first DQ line, while the results of on-chip comparison can be sampled at the second DQ line.
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Fuller Paul M.
Wright Jeffrey P.
Zheng Hua
Abraham Esaw
Cady Albert De
Micron Technology Inc
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