Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1999-08-03
2003-04-22
DeCady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S201000
Reexamination Certificate
active
06553520
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit devices and methods of operation thereof, and more particularly, to apparatus and methods for testing integrated circuit devices.
BACKGROUND OF THE INVENTION
In order to ensure reliability and proper operation of integrated circuit devices, such as memory devices, manufacturers typically perform a variety of tests on internal circuits in the devices. An example of such a test is a bit line sensing test, which is usually important in verifying proper operation of an integrated circuit memory device such as a DRAM.
A typical bit line sensing process is performed as follows. Data stored in a memory cell is transmitted to a bit line through a charge sharing operation performed by the activation of the word line connected to the memory cell. A difference between the voltage of the bit line to which the data of the memory cell is transmitted and the precharge voltage of a complementary bit line is amplified by a sense amplifier, producing a signal with a logic “high” or “low” value. The time at which the sense amplifier operates typically is critical to the operation of the memory device. In order to improve the operating characteristics of the semiconductor device, it is generally important that the sense amplifier operates at an optimal or near optimal time. Therefore, memory devices commonly include a test mode for determining the time at which the sense amplifier operates in response to a test signal applied to a pad of the integrated circuit memory device.
Another common test for a memory device involved determining whether voltage generating circuits of the device operate appropriately. Many kinds of internal voltage generating circuits may be used in memory devices. Test pads may be also be provided in the integrated circuit chip for testing the various internal voltage generating circuits at the wafer stage.
It generally is infeasible to connect such internal test signal pads to external leads when the integrated circuit device is packaged, however, due to limitations on the number of available external leads. Consequently, pads for applying test signals or for monitoring signals may not be connected to external leads of the packaged device.
SUMMARY OF THE INVENTION
In light of the foregoing, it is an object of the present invention to provide packaged integrated circuit devices and operating methods that allow for testing of internal functions from external signal leads.
This and other objects, features and advantages are provided according to the present invention by integrated circuit devices and operating methods in which an external signal lead of a packaged integrated circuit device is coupled to an integrated circuit chip including a mode-selective signal generating circuit that is operative to generate a signal responsive to either an external signal applied to the external signal lead or an internal signal generated by a signal generating circuit on the chip. According to an embodiment of the present invention, a sense enable signal for a memory sense amplifier is generated responsive to one of an external signal applied to an external lead or an internal sense enable control signal generated on the chip. According to another embodiment of the present invention, a reference voltage is generated responsive to one of an external signal applied to an external lead or an internally generated reference voltage.
In particular, according to the present invention, an integrated circuit device includes a package and an externally accessible signal lead attached to the package. An integrated circuit chip is mounted in the package and connected to the signal lead. The integrated circuit chip includes a mode-selective signal generating circuit configured to receive a mode control signal and an internal signal and coupled to the externally accessible signal lead. The mode-selective signal generating circuit is operative to produce an output signal responsive to one of the internal signal or an external signal applied to the externally accessible signal lead based on the mode control signal.
According to an embodiment of the present invention, the integrated circuit chip further includes a memory circuit including a sense amplifier that senses a bit line voltage in response to a sense enable signal. The internal signal includes a sense enable control signal having a timing adapted for sensing a bit line voltage in a memory cycle of the memory circuit. The mode-selective signal generating circuit is operative to generate the sense enable signal responsive to one of the sense enable control signal or the external signal based on the mode control signal. The mode-selective signal generating circuit may be operative to generate the sense enable signal responsive to the sense enable control signal when the mode control signal is in a first state and to generate the sense enable signal responsive to the external signal when the mode control signal is in a second state.
According to a related aspect of the present invention, the chip further includes a conductive pad electrically connected to the mode-selective gating circuit. The mode-selective signal generating circuit is operative to generate the sense enable signal responsive to one of the sense enable control signal or a signal applied to the conductive pad based on the mode control signal.
According to yet another embodiment, the mode-selective gating circuit includes a selective test signal generating circuit connected to the externally accessible signal lead and to the conductive pad and operative to generate a test signal responsive to one of an external signal applied to the externally accessible signal lead and a signal applied to the conductive pad. A gating circuit configured to receive the test signal, the sense enable control signal and the mode control signal, and operative to generate the sense enable signal responsive to one of the test signal and the sense enable control signal based on the mode control signal. The selective test signal generating circuit may include a first NAND gate configured to receive the mode control signal and the external signal at inputs thereof and to produce an output signal therefrom at an output of the first NAND gate, a second NAND gate having a first input connected to the output of the first NAND gate, a pulldown transistor connected between the conductive pad and a signal ground, and an inverter having an input connected to the conductive pad and an output connected to a second input of the second NAND gate. The second NAND gate generates the test signal at an output thereof.
According to another aspect of the present invention, the chip further includes a mode control signal generating circuit operative to generate the mode control signal. The mode control signal generating circuit may be responsive to a reset signal, a test reset signal, and an address signal. The mode control signal generating circuit may be operative to reset the mode control signal to the first state in response to the reset signal and to latch the mode control signal to a value dependent upon a value of the address signal when the test reset signal is asserted.
In yet another embodiment, the internal signal includes an internally-generated reference signal produced at a reference signal bus, and the mode-selective signal generating circuit includes a transfer gate coupling the externally accessible signal lead to the reference voltage node and operative to apply a voltage applied to the externally accessible signal lead to the reference signal bus responsive to the mode control signal.
Related operating methods are also provided.
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patent: 2 327 506 (1999-01-
DeCady Albert
Harris Cynthia
Myers Rigel Sibley & Sajovec
Samsung Electronics Co,. Ltd.
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