Integrated circuit memory devices including internal stress...

Details Integrated circuit memory devices including internal stress... Integrated circuit memory devices including internal stress...

1998-09-16

2001-05-01

Moise, Emmanuel L. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S721000, C365S201000

Reexamination Certificate

active

06226764

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to integrated circuit memory devices and testing methods therefor, and more particularly to built-in self test (BIST) circuits and methods for integrated circuit memory devices.
BACKGROUND OF THE INVENTION
Integrated circuit memory devices are widely used in consumer and commercial electronics. As is well known to those having skill in the art, integrated circuit memory devices generally include a memory cell array and peripheral circuits for reading data from, writing data to, and controlling the memory cell array.
As the size of the memory cell array continues to increase, it may become increasingly difficult to test the memory cell array. In particular, in order to test the memory cell array, a large number of test patterns may be provided to the memory cell array, and the response of the memory cell array to the test patterns may be monitored. This testing may be time-consuming and may use all of the input/output pins of the integrated circuit memory device, which may thereby limit the number of memory devices that may be tested simultaneously. Accordingly, it is known to provide a memory test pattern and control circuit in the integrated circuit memory device itself, in order to provide Built-In Self Test (BIST). More specifically, a BIST unit in the integrated circuit memory device may include a memory test pattern that is used to perform the BIST.
It is also generally known to provide stress testing of the memory cell array by applying a stress voltage that is larger than the internal supply voltage of the integrated circuit memory device, to the memory, while performing the BIST on the memory cell array. However, it may be difficult to supply the stress voltage to the memory cell array while performing the BIST on the memory cell array. Moreover, application of the stress voltage may damage the integrated circuit memory device. Finally, separate burn-in testers may be needed to test the memory using a stress voltage.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved integrated circuit memory devices and Built-In Self Test (BIST) circuits and methods therefor.
It is another object of the present invention to provide improved circuits and methods for performing stress BIST for integrated circuit memory devices.
These and other objects are provided, according to the present invention, by integrated circuit memory devices that include a stress voltage generator that generates a stress voltage that is higher than the internal supply voltage of the integrated circuit memory device and that applies the stress voltage to the memory cell array during the stress BIST of the memory cell array. The stress voltage generator is preferably responsive to a BIST request signal and to a stress test signal that are applied from external of the integrated circuit memory device, to apply the stress voltage to the memory cell array and to perform a BIST of the memory cell array. The stress voltage generator is responsive to the BIST request signal and absence of the stress test signal, to apply the internal supply voltage to the memory cell array and to perform a BIST of the memory cell array. Accordingly, circuits within the integrated circuit memory device can be responsive to external test signals to generate stress voltages during BIST.
Integrated circuit memory devices according to the invention may also include a stress controller that is responsive to the stress test signal that is applied from external of the integrated circuit memory device, to control the stress voltage generator. A BIST unit is responsive to the BIST request signal that is applied from external of the integrated circuit memory device, to perform the BIST of the memory cell array.
The stress voltage generator preferably includes an internal supply voltage generator that generates the stress voltage from a reference voltage, and a clamping unit that clamps the stress voltage to the internal supply voltage in response to a control signal. A stress controller is responsive to the stress test signal that is applied from external of the integrated circuit memory device, to disable the control signal.
Accordingly, in order to stress BIST a memory cell array, a stress voltage is generated that is higher than the internal supply voltage of the integrated circuit memory device. The stress voltage is applied to the memory cell array and stress built-in self testing of the memory cell array is performed simultaneously.
According to another aspect of the invention, various externally controlled and BIST tests may be performed on an integrated circuit memory device by performing the following steps in the integrated circuit memory device in response to an external signal. A determination is made as to whether the integrated circuit memory device is in normal BIST mode or in stress BIST mode in response to the external signal. BIST is performed on the memory cell using an internal supply voltage if the memory is in normal BIST mode. Alternatively, a stress voltage that is higher than the internal supply voltage is generated and BIST is performed on the memory cell array using the stress voltage if the memory is in stress BIST mode. A determination is also made as to whether the integrated circuit memory device is in an externally controlled test mode in response to the external signal. The memory cell array is tested under external control if the integrated circuit memory device is in the externally controlled test mode.
In the external test mode, a determination may be made as to whether the integrated circuit memory device is in an externally controlled normal test mode or in an externally controlled direct access test mode. The memory cell array may be tested normally if the integrated circuit memory device is in the externally controlled normal test mode. The memory cell array may be directly accessed and tested if the integrated circuit memory device is in the externally controlled direct access test mode. Accordingly, normal BIST and stress BIST may be performed internal to the memory device under control of external mode signals.


REFERENCES:
patent: 5265057 (1993-11-01), Furuyama et al.
patent: 5298433 (1994-03-01), Furuyama
patent: 5315598 (1994-05-01), Tran
patent: 5381373 (1995-01-01), Ohsawa
patent: 5404099 (1995-04-01), Sahara
patent: 5424988 (1995-06-01), McClure et al.
patent: 5638331 (1997-06-01), Cha et al.
patent: 5654925 (1997-08-01), Koh et al.
patent: 5657282 (1997-08-01), Lee
patent: 5825785 (1998-10-01), Barry et al.
patent: 5973981 (1999-10-01), Lee
patent: 6031773 (2000-02-01), Taylor
patent: 40313984 (1991-06-01), None

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