I/O compression circuit for a semiconductor memory device

Details I/O compression circuit for a semiconductor memory device I/O compression circuit for a semiconductor memory device

2005-08-23

2005-08-23

Sheikh, Ayaz (Department: 2131)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S718000, C714S719000, C714S726000, C365S200000, C365S201000, C365S189011, C365S230010, C365S230030, C324S765010, C324S800000, C324S800000

Reexamination Certificate

active

06934895

ABSTRACT:
An I/O compression circuit for a semiconductor memory device operates in a same data compress mode to transmit identical data to all compressed data buses and a different data compress mode to transmit different data to adjacent compressed data buses.

REFERENCES:
patent: 5864510 (1999-01-01), Nakaoka
patent: 6009026 (1999-12-01), Tamlyn et al.
patent: 6357027 (2002-03-01), Frankowsky
patent: 6452845 (2002-09-01), Merritt
patent: 7-85699 (1995-03-01), None
Notice of Rejection from Korean Intellectual Property Office dated Dec. 8, 2003 (4 pages).

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