Integrated circuit test mode with externally forced reference vo

Details Integrated circuit test mode with externally forced reference vo Integrated circuit test mode with externally forced reference vo

1998-02-10

2000-09-12

De Cady, Albert

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

365201, G11C 2900

Patent

active

06119252&

ABSTRACT:
A memory device is described which includes a latch circuit for latching a normally externally provided signal during a test mode. The input pin which is normally enabled to receive the external signal is re-routed to provide an external reference voltage, Vref, to internal circuitry. During testing operations the external Vref signal is used. Once an integrated circuit is determined to be good, an internal generator circuit is set to provide Vref. The integrated circuit can be a flash memory device, and the input pin can be a BYTE command pin. This method of substituting the source of Vref eliminates time required to set the internal generator circuit in defective memory devices.

REFERENCES:
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patent: 5526364 (1996-06-01), Roohparvar
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"Flash Memory 2 Meg X 8", Flash Memory Data Book, Micron Quantum Devices, Inc., 2-5:2-33, (1997).

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