Input/output compression test circuit

Details Input/output compression test circuit Input/output compression test circuit

2007-01-30

2007-01-30

DeCady, Albert (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S734000, C714S718000, C714S048000, C714S030000, C365S201000

Reexamination Certificate

active

10734132

ABSTRACT:
The I/O compression test circuit performs test on global I/O lines divided into groups after failure occurs, thereby improving repair efficiency. The configuration of the test circuit is simplified by using a reset circuit, reducing the delay time, and thereby decreasing test time. Additionally, two strobe signals enable the I/O compression test circuit to perform a stable operation.

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