Low-consumption TTL-CMOS input buffer stage
Low-jitter adjustable level shifter with native devices and...
Low-jitter high-frequency clock channel
Low-latency small-swing clocked receiver
Low-latency small-swing clocked receiver
Low-leakage integrated circuits and dynamic logic circuits
Low-leakage level shifter with integrated firewall and method
Low-leakage level shifter with integrated firewall and method
Low-leakage level shifter with integrated firewall and method
Low-leakage level shifter with integrated firewall and method
Low-noise output buffer
Low-noise PECL output driver
Low-power 5 volt tolerant input buffer
Low-power CMOS digital voltage level shifter
Low-power consumption bi-CMOS circuit formed by a small number o
Low-power output driver buffer circuit
Low-power routing multiplexers
Low-power semi-dynamic flip-flop with smart keeper
Low-power transceiver architectures for programmable logic...
Low-power, compact digital logic topology that facilitates large