Low-power semi-dynamic flip-flop with smart keeper

Details Low-power semi-dynamic flip-flop with smart keeper Low-power semi-dynamic flip-flop with smart keeper

2008-07-25

2009-12-08

Le, Don P (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S093000, C326S046000

Reexamination Certificate

active

07629815

ABSTRACT:
A modified high-speed flip-flop including an input circuit, a smart window circuit, a smart keeper circuit, a pre-charge circuit, a discharge circuit, a slave storage circuit, and an output circuit. Additionally, a circuit including the modified high-speed flip-flop, the circuit also including a non-zero operating voltage provided to the flip-flop, a common voltage provided to the flip-flop, a clock signal input to the flip-flop, a data signal input to the flip-flop wherein the data signal has a high state and a low state, and an output signal from the flip-flop wherein the output signal has a high state and a low state.

REFERENCES:
patent: 7161390 (2007-01-01), Aipperspach et al.
patent: 7282957 (2007-10-01), Sumita
patent: 2003/0110404 (2003-06-01), Seningen et al.
patent: 2008/0106302 (2008-05-01), Sit et al.

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