Low-power 5 volt tolerant input buffer

Details Low-power 5 volt tolerant input buffer Low-power 5 volt tolerant input buffer

1996-11-12

1999-03-09

Santamauro, Jon

Electronic digital logic circuitry

Interface

Current driving

326 83, 326 81, H03K 190185

Patent

active

058806059

ABSTRACT:
The present invention is directed to a low-power input buffer comprising an inverter coupled to receive a first safe voltage range to a first node and coupled to provide an output signal, and a low-power circuit coupled to receive a second safe voltage range and coupled to control a voltage at the first node in response to the output signal and the second safe voltage range. The first and second safe voltage ranges preferably are equivalent. The low-power circuit includes series transistors coupled to the first node and responsive to the voltage at the output node. The low-power circuit further includes a transistor coupled between the first and second nodes and responsive to an input voltage. A method of operating an input buffer comprises the steps of pulling up a voltage of a first node in response to voltages of a second node and an output node and pulling down the voltage at the first node and the second node in response to an input voltage to provide low power consumption and a high impedance input.

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