Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2002-10-28
2004-05-18
Le, Don P (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S087000, C326S027000
Reexamination Certificate
active
06737886
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the field of integrated circuits, and more specifically to an output buffer.
2. Description of Related Art
Output buffers are used in integrated circuits (“ICs” in the following) for driving signal lines connected to the signal outputs of the IC. For example, in semiconductor memory ICs output buffers are associated with the data outputs and are used to drive data bus lines external to the memory.
As known from the technical literature, to a first approximation the signal line can represented in a schematic by a capacitive load for the IC signal output. The amount of the capacitive load depends on the parasitic capacitance associated with the signal line connecting the IC signal output to signal inputs of different ICs and on the fan-out of the signal output (i.e., the number of such signal inputs).
The requirements in terms of driving capability of the output buffers are in general rather severe. For example, an output buffer of a Flash memory IC must be capable of driving loads of 30 pF or more. This has a significant impact on the operating speed of the output buffer.
In the past, the operating speed of the output buffers was not a major concern, at least as far as Flash memory ICs were considered. Operating frequencies of the order of 50 MHz were considered sufficient, so that the relatively low speed of the output buffer had not a great impact.
Nowadays, with the enormous performance increase of microprocessors, the operating speed requirements for the memory ICs have consequently become more demanding. Manufacturers have thus started to offer memories operating at 100-150 MHz.
In view of this, the relatively low speed of the output buffers represents now one of the bottlenecks in achieving higher IC speeds, in particular for Flash memory ICs.
In order to increase the speed of the output buffer, the output buffer must be capable of delivering (i.e., supplying or sinking) a relatively large current in a short time. Relatively high current time derivatives are thus involved.
To study the behaviour of the output buffer, a correct electrical model of the IC package is adopted. In general, each contact pad of the IC, be it a signal input or output contact pad or a voltage supply contact pad (VDD or GND), is connected through a bonding wire to a package lead, terminating with a pin for the electrical and mechanical connection to a conductive track of a printed circuit board (PCB). Taking into account the parasitic components and adopting a lump-parameter model, conventionally called “reverse &Ggr;” model, each voltage supply input of the IC can be schematised as connected to the respective voltage supply track of the PCB through the series of a resistor and an inductor; the capacitance present in the reverse &Ggr; model can be neglected, since the potential of the supply voltage tracks can be assumed to be time-invariable. Similarly, each signal output can be schematised as connected to a capacitive load through the series of a resistance and an inductor; in this case, the capacitance present in the reverse &Ggr; model simply adds up to the capacitive load. The parasitic resistor, normally of quite small resistance, causes a small voltage drop, which is proportional to the current circulating through it. However, when the current time derivatives become significant, the skin effect can cause an increase of the parasitic resistance, with the consequence of slowing down the transitions between logic states and inducing noise on the effective supply voltages at the IC contact pads. More problems come however from the parasitic inductor, which introduces a voltage drop directly proportional to the time derivative of the current flowing through it. This slows down the transitions between logic states and causes irradiation of noise throughout the circuitry due to cross-talks. In the worst case, logic errors can be induced such as, in a memory IC, the start of a spurious read operation. This kind of noise is the most feared, because it increases with the increase of the output buffer speed.
The solutions proposed in the art to the above-discussed problem are of two kinds.
According to a first solution, the output buffer, in principle an inverter, is made up of a plurality of parallel-connected pull-up and pull-down transistors of relatively small resistance. When the output buffer has to switch the associated output line from one logic state to the other, the transistors are selectively turned on according to a prescribed timing. In this way, the maximum current that can be delivered by the output buffer is equal to that deliverable by an output buffer having only one pull-up and one pull-down transistor of large resistance, but the current time derivative can be kept sufficiently small.
A second solution provides for slowing down the pull-up and pull-down transistors turning on, so as to limit the current time derivative.
This two solutions are normally encountered in every output buffer, either alone or combined together and possibly in combination with further techniques for a feed-back or adaptive control of other conditions such as process variations, temperature and so on.
Although the solutions outlined above are useful, they have however proved not sufficient to solve the problem of the output buffer-induced switching noise. A further measure adopted by almost all the manufacturers of ICs consists in splitting the voltage supplies for the output buffers from those for the remaining circuitry of the IC. By way of example, memory devices are commercially available in which dedicated voltage supply contact pads (VDD and GND) are provided every two output buffers.
This solution, albeit rather drastic in reducing the switching noise problem, has the disadvantage of causing a substantial increase in the IC chip size, and thus of production costs, because each contact pad occupies a significant area. Additionally, dedicated packages must be designed, having a higher number of pins than standard ones. Apart from the intrinsic higher costs of a dedicated package compared to a standard one, the end users have to redesign the PCBs on which the ICs are to be mounted.
SUMMARY OF THE INVENTION
The present invention provides an output buffer capable of reaching high operating speeds, featuring a low noise and not affected by the drawbacks of the known output buffers. An output buffer according to one aspect of the present invention comprises a current path switch circuit activatable for causing a prescribed current to constantly flow between a first voltage line and a second voltage line during a time between two successive switchings of the output line, and for causing the prescribed current to be deviated to the output line during at least an initial phase of an output line switching from the first voltage line voltage to the second voltage line voltage or vice versa. A current delivered by that voltage line, between the first and second voltage lines, which plays an active role in the output line switching is thus kept substantially constant.
In this way, when the output line voltage must be switched from the voltage of the first voltage line to the voltage of the second voltage line, or vice versa, the time derivative of the current flowing between the first and second voltage lines is kept small. The switching noise caused by the presence of parasitic components such as inductances associated with the bonding wire and the package lead is minimized.
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European Search Report dated Feb. 25, 2002 for European Application No. 01830675.
Curatolo Giacomo
Martines Ignazio
Torrisi Davide
Fleit, Kain, Gibbons, Gutman, Bongini & Blanco P.L.
Gibbons Jon A.
Le Don P
STMicroelectronics S.r.l.
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