Low-power transceiver architectures for programmable logic...

Details Low-power transceiver architectures for programmable logic... Low-power transceiver architectures for programmable logic...

2008-07-22

2008-07-22

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S037000, C326S086000

Reexamination Certificate

active

07403035

ABSTRACT:
High-speed serial interface or transceiver circuitry on a programmable logic device integrated circuit (“PLD”) includes features that permit the PLD to satisfy a wide range of possible user needs or applications. This range includes both high-performance applications and applications in which reduced power consumption by the PLD is important. In the latter case, any one or more of various features can be used to help reduce power consumption.

REFERENCES:
patent: 6617877 (2003-09-01), Cory et al.
patent: 2005/0058186 (2005-03-01), Kryzak et al.
U.S. Appl. No. 11/725,653, filed Mar. 19, 2007, Shumarayev et al.
U.S. Appl. No. 11/295,391, filed Dec. 5, 2005, Shumarayev et al.

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