Low-power, compact digital logic topology that facilitates large

Details Low-power, compact digital logic topology that facilitates large Low-power, compact digital logic topology that facilitates large

1995-11-22

1997-09-23

Hudspeth, David R.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326 21, 326121, H03K 19017

Patent

active

056708980

ABSTRACT:
A circuit topology for implementing combinational logic functions with large fan-in, high speed, and low power consumption using a combination of dynamic and static gates. The circuit topology includes a dynamic gate and a Pseudo-NMOS gate coupled to the dynamic gate.

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Yuan, Jiren and Christer Svensson, "High-Speed CMOS Circuit Technique", IEEE Journal of Solid-State Circuits, vol. 24, No. 1, pp. 62-70, Feb. 1989 .

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