Low-consumption TTL-CMOS input buffer stage

Details Low-consumption TTL-CMOS input buffer stage Low-consumption TTL-CMOS input buffer stage

1998-12-30

2001-10-23

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Logic level shifting

C326S082000, C326S058000, C326S083000, C326S068000

Reexamination Certificate

active

06307396

ABSTRACT:

TECHNICAL FIELD
This invention relates to a novel configuration of an input buffer which is capable of effecting conversions between TTL and CMOS logic levels, while complying with low supply consumption specifications.
More particularly, the invention relates to a low-consumption TTL-CMOS input buffer stage of the type which comprises a chain of inverters cascade connected between an input, receiving electric signals at a TTL logic level, and an output reproducing electric signals at a CMOS logic level the inverters being powered between a first or supply voltage reference and a second or ground reference.
BACKGROUND OF THE INVENTION
As those skilled in the art will recognize, many electronic circuits integrated by CMOS technology require that electric signals at a TTL logic level are received as input from TTL logic circuitry.
In each CMOS circuit having TTL inputs, the input buffer stage is asked to effect a conversion of logic levels. As a result of this conversion, the internal circuitry will receive signals which are purely CMOS but logically congruous with the TTL inputs of the integrated circuit.
In this respect, it should be remembered that, in TTL logics, an input signal is regarded to have a “low” logic value if the signal amplitude is less than 0.8V, and to have a “high” logic value if the signal amplitude exceeds 2.0V.
These conditions must be complied with regardless of the internal supply voltage of the input buffer.
The accompanying
FIG. 1
shows a circuit diagram of a conventional input buffer stage
1
for TTL-CMOS conversion, in its simplest form.
The buffer
1
is basically formed by a chain of inverters which are all supplied by same device internal supply voltage Vcc. The aspect ratio of the first inverter
2
in the chain is unbalanced to lower its threshold, while the last two inverters in the chain, indicated with
3
and
4
, have an aspect ratio of (Wp/Lp)/(Wn/Ln)=2 to ensure that the rising and falling edges of the output signal OUT, to be passed to downstream circuitry, will be identical.
It should be noted that the changeover threshold of the circuit
1
in
FIG. 1
increases linearly with the supply voltage Vcc, as shown in FIG.
1
A. Furthermore, the threshold sweep, for a sweep &Dgr; of the voltage V, is bound to be &Dgr;/2 regardless of the aspect ratii of the inverters in the chain.
This feature restricts the margin for noise of the structure with a high input. In fact, this margin is by definition:
NM
H
=2.0
−V
Th(Vcc)
and, therefore, mini while Vcc is at a maximum.
But the structure shown in
FIG. 1
has another problem: it has been found that, for a TTL input, the NMOS and PMOS transistors of the first inverter
2
are both in the ‘on’ state. This means that, while still ensuring that the circuit output OUT is at its specified logic level, a high current consumption occurs, especially when the supply voltage Vcc is at the highest value provided for by the specifications.
A typical static consumption of tens of microamperes has been found for a single buffer. This consumption is unacceptable, especially in circuits that are to be incorporated into low-power amplifiers which often require that, following a time latency of the inputs, the circuit goes to a standby state of low consumption and is prepared for a new switching.
The state of the art proposes a second solution to fill the demand for TTL-CMOS conversion. Shown schematically in
FIG. 2
is an input buffer stage
5
which is again configured as an inverter chain and includes a current generator
6
for controlling the switching threshold in a high supply voltage situation.
While being in many ways advantageous, not even this solution is entirely satisfactory, again by reason of its excessively high consumption.
In fact, the first inverter
7
in the chain is supplied the voltage Vcc through a PMOS transistor M
1
connected to the current generator
6
. Since the current through the first inverter
7
is limited by M
1
, especially at high supply voltages, the rise in the switching threshold will be reduced even as Vcc increases, as shown in FIG.
2
A. Thus, the margin for noise is improved in the circuit
5
.
However, the static consumption of the bias network of the gate terminal of the transistor M
1
adds to that of the inverter chain.
SUMMARY OF THE INVENTION
An embodiment of this invention provides a novel structure of a TTL-CMOS input buffer stage which has such constructional and functional features as to ensure lower consumption than the solutions proposed by the prior art.
This allows incorporation of the input buffer stage to any types of CMOS circuits requiring conversion from TTL logic levels and being intended for low-power applications.
The embodiment has the first inverter in the buffer sized symmetrically with its pull-up and pull-down portions, and further providing two signal paths, one for normal operation and the other for low-consumption operation.


REFERENCES:
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patent: 4469959 (1984-09-01), Luke et al.
patent: 4642488 (1987-02-01), Parker
patent: 4929853 (1990-05-01), Kim et al.
patent: 5144167 (1992-09-01), McClintock
patent: 5151620 (1992-09-01), Lin
patent: 5341046 (1994-08-01), Crafts
patent: 5614847 (1997-03-01), Kawahara et al.
patent: 595318 A2 (1994-05-01), None
patent: 621694 A2 (1994-10-01), None
patent: 05304464 A (1993-11-01), None

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