Thread-aware instruction fetching in a multithreaded...

Thread-specific branch prediction by logically splitting...

Three input arithmetic logic unit with barrel rotator and mask g

Three input arithmetic logic unit with shifter

Three input arithmetic logic unit with shifter and mask generato

Three level direct communication connections between...

Three operand instruction extension for X86 architecture

Three state branch history using one bit in a branch...

Three-dimensional networking structure

Threshold-based load address prediction and new thread...

Throwing one selected representative exception among...

Tiered sequential processing media data through multiple...

Tightly coupled accelerator

Time-multiplexed speculative multi-threading to support...

Time-of-life counter design for handling instruction flushes...

Time-of-life counter for handling instruction flushes from a...

Token-based storage for general purpose processing

Total flexibility of predicted fetching of multiple sectors...

Touch history table

Trace branch prediction unit