Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Patent
1998-09-17
2000-10-31
Coleman, Eric
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
709247, 710 3, G06F 1200
Patent
active
061417432
ABSTRACT:
The present invention discloses a system and method for compressing data transmitted over a bus between a bus device, such as a CPU or an I/O device, and a memory subsystem. The data is compressed into data tokens and the tokens are stored in and retrieved from the memory subsystem. The CPU may also contain a token-generating circuit. Content addressable memory is employed to compare the data against expected bit patterns for generating the data tokens. Upon encountering a match, the content addressable memory returns the data token associated with the matching bit pattern. Both the bus device and memory subsystem may have the capability to compress data into tokens and re-expand data when necessary. A method is also employed for indicating to a device receiving data whether the data is a token or not.
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Advanced Micro Devices , Inc.
Coleman Eric
Kivlin B. Noel
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