Trace branch prediction unit

Details Trace branch prediction unit Trace branch prediction unit

1997-12-31

2000-01-11

Treat, W.

Electrical computers and digital processing systems: processing

Processing control

Branching

712233, 712238, 712239, 712240, G06F 938

Patent

active

060147423

ABSTRACT:
A trace branch prediction unit includes a trace branch target buffer connected to a trace cache. The trace cache stores traces of micro-ops, with the micro-ops being stored non-sequentially. The trace branch target buffer generally reads a buffer entry corresponding to a particular trace line one clock cycle before the trace line is read to a processor. Using the entry, the trace branch target buffer predicts whether the trace cache should follow the existing trace or leave the trace. If the trace branch target buffer predicts that the trace cache should leave a trace, the trace branch target buffer provides a target address for a new trace. The trace branch target buffer also predicts when a trace is ending and provides a target address for the next trace.

REFERENCES:
patent: 5381533 (1995-01-01), Peleg et al.
patent: 5742804 (1998-04-01), Yeh et al.
Dutta et al., "Control Flow Prediction with Tree like Sudgraphs for Superscalar Processors", Proceedings of the 28th Annual International Symposium on Microarchitecture, 1995, IEEE, pp. 258-263, Nov. 29-Dec. 1, 1995.
Patt et al., "One Billion Transistors, One Uniprocessor, One Chip", Computer, IEEE, vol. 30, iss. 9, pp. 51-57, Sep. 1997.
Jacobsen et al., "Path-based Next Trace Prediction", Proceedings of Thirtieth Annual IEEE/ACM Symposium on Microarchitecture, pp. 14-23, Dec. 1-3, 1997.
Jacobsen et al., "Control Flow Speculation in Multiscalar Processors", Third International Symposium on High-Performance Computer Architecture, IEEE, pp. 218-229, Feb. 1-5, 1997.
Rotenberg et al., "Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching", Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, Dec. 2-4, 1996.

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