Thread-specific branch prediction by logically splitting...

Details Thread-specific branch prediction by logically splitting... Thread-specific branch prediction by logically splitting...

2006-10-10

2006-10-10

Chan, Eddie (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Branching

C712S238000, C712S239000, C712S229000

Reexamination Certificate

active

07120784

ABSTRACT:
Branch prediction logic is enhanced to provide a monitoring function for certain conditions which indicate that the use of separate BHTs and predicted target address cache would provide better results for branch prediction. The branch prediction logic responds to the occurrence of the monitored condition by logically splitting the BHTs and count cache so that half of the address space is allocated to a first thread and the second half is allocated to the next thread. Prediction-generated addresses that belong to the first thread are then directed to the half of the array that is allocated to that thread and prediction-generated addresses that belong to the second thread are directed to the next half of the array that is allocated to the second thread. In order to split the array, the highest order bit in the array is utilized to uniquely identify addresses of the first and the second threads.

REFERENCES:
patent: 2001/0056456 (2001-12-01), Cota-Robles
patent: 2003/0004683 (2003-01-01), Nemawarkar
Research Disclosure, Jun. 1, 1998, UK. vol. 41, Issue 410. TDB Acc No. NNR410111.
Hilly, S., Seznec, A. “Branch Prediction and Simultaneous Multithreading” Proceedings of PACT 1996. pp. 169-173.
Ramsay, M., Feucht, C., Lipasti, M. “Exploring Efficient SMT Branch Predictor Design.” Jun. 2003. 13 pages.

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