Tiered sequential processing media data through multiple...

Details Tiered sequential processing media data through multiple... Tiered sequential processing media data through multiple...

2007-10-02

2007-10-02

Kim, Kenneth S. (Department: 2111)

Electrical computers and digital processing systems: processing

Processing architecture

Array processor

C713S502000, C718S102000

Reexamination Certificate

active

11095201

ABSTRACT:
Tiered command distribution is described. In an embodiment, a pipeline architecture includes processor chains of data processors that process control events received from an application interface control. A tier assignment algorithm determines the longest path of data processors through the processor chains to determine a tier allocation for each data processor in the set of processor chains. Each tier includes a data processor from one or more of the processor chains where a first set of data processors in a first tier each receive a control event and process the control event and/or process the data according to the control event before a second set of data processors in a second tier each receive the control event.

REFERENCES:
patent: 5317735 (1994-05-01), Schomberg
patent: 6119215 (2000-09-01), Key et al.
patent: 2005/0204215 (2005-09-01), Tukiainen

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