Three operand instruction extension for X86 architecture

Details Three operand instruction extension for X86 architecture Three operand instruction extension for X86 architecture

2007-12-12

2010-11-16

Coleman, Eric (Department: 2183)

Electrical computers and digital processing systems: processing

Instruction decoding

Decoding instruction to accommodate plural instruction...

C712S210000

Reexamination Certificate

active

07836278

ABSTRACT:
A method and apparatus are contemplated for increasing the number of available instructions in an instruction set architecture. The new instructions extend the number of general-purpose registers and include three or more operands. A combination of an escape code field, an opcode field, an operation configuration field and an operation size field determines a unique new instruction operation. A source operand extension field includes bits to be combined with other fields in order to extend the number of source operand values for general-purpose registers.

REFERENCES:
patent: 6049863 (2000-04-01), Tran et al.
patent: 6141745 (2000-10-01), Pickett
patent: 6157996 (2000-12-01), Christie et al.
patent: 6275927 (2001-08-01), Roberts
patent: 6571330 (2003-05-01), McGrath et al.
patent: 6625724 (2003-09-01), Kahn et al.
patent: 6981132 (2005-12-01), Christie et al.
patent: 7302551 (2007-11-01), Henry et al.
patent: 2004/0268090 (2004-12-01), Coke et al.
U.S. Appl. No. 11/944,870; filed Dec. 30, 2004.

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