Three input arithmetic logic unit with shifter and mask generato

Details Three input arithmetic logic unit with shifter and mask generato Three input arithmetic logic unit with shifter and mask generato

1993-11-30

1999-10-26

Lall, Parshotam S.

Electrical computers and digital processing systems: processing

Processing control

Arithmetic operation instruction processing

712224, 708236, G06F 9302, G06F 9315

Patent

active

059745398

ABSTRACT:
A three input arithmetic logic unit (230) generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shift (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal. This mask input signal may be the default shift amount or a predetermined number of the least significant bits of the third input signal as selected by a multiplexer. A second preferred form of the mask is selected one of the left most 1, the right most 1, the left most bit change or the right most bit change of a predetermined set of the least significant bits of data recalled from a data register.

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