Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
2005-01-31
2008-03-25
Meonske, Tonia L. (Department: 2181)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C712S218000
Reexamination Certificate
active
07350055
ABSTRACT:
An accelerator120is tightly coupled to the normal execution unit110. The operand store, which could be a register file130, a stack based operand store or other operand store is shared by the execution unit and the accelerator unit. Operands may also be accessed as immediate values within the instructions themselves. The sequences of individual program instructions corresponding to computational subgraphs remain within a program but can be recognized by the accelerator as suitable for acceleration and when encountered are executed by the accelerator instead of by the normal execution unit. Within such tightly coupled arrangement problems can arise due to a lack of register resources within the system. The present technique provides that at least some intermediate operand values which are generated within the accelerator, but are determined not to be referenced outside of the computational subgraph concerned, are not written to the operand store.
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Biles Stuart D.
Clark Nathan
Flautner Krisztian
Mahlke Scott
Arm Limited
Meonske Tonia L.
Nixon & Vanderhye P.C.
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