PCI-to-PCI bridges with a timer register for storing a delayed t

Peak power reduction when updating future file

Performance enhancement for code transitions of floating...

Performance evaluation apparatus, performance evaluation...

Performance monitoring based on instruction sampling in a...

Performance monitors in a multithreaded processor architecture

Performing pending interrupts or exceptions when interruptible j

Performing repeat string operations

Performing SIMD shift and arithmetic operation in non-SIMD archi

Performing variable and/or bitwise shift operation for a...

Physical rename register for efficiently storing floating...

Physical rename register for efficiently storing floating...

Pipe scheduling for pipelines based on destination register...

Pipeline accelerator including pipeline circuits in...

Pipeline computer dividing a variable-length data-handling...

Pipeline computer with a scoreboard control circuit to prevent i

Pipeline control for high-frequency pipelined designs

Pipeline controller for context-based operation...

Pipeline controller for providing independent execution...

Pipeline data processing apparatus of reduced circuit scale