PCI-to-PCI bridges with a timer register for storing a delayed t

Details PCI-to-PCI bridges with a timer register for storing a delayed t PCI-to-PCI bridges with a timer register for storing a delayed t

1998-03-17

2000-02-01

An, Meng-Ai T.

Electrical computers and digital processing systems: processing

Processing architecture

Distributed processing system

712 28, 712 31, 712 33, 712 37, 712 38, 712 40, 710 62, 710101, 710107, 710129, 710250, 710262, G06F 1300

Patent

active

06021483&

ABSTRACT:
To improve the efficiency of delayed transactions in bus-to-bus bridge systems which include at least one interface to a PCI bus, a bridge system is disclosed including at least a primary interface and an interface to a secondary subsystem for interconnecting a primary PCI bus system and the secondary subsystem. The system comprises a delayed transaction mechanism for enabling a transaction source attached to the primary PCI bus system to effect delayed transactions with a target in the secondary subsystem. This system has a programmable delay transaction timer which provides a degree of flexibility in the configuration of PCI systems. This flexibility can be exploited to provide considerable efficiency gains, albeit at the expense of some deviation of the strict requirements of the PCI Specification.

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patent: 5884027 (1999-03-01), Garbus et al.
patent: 5911084 (1999-01-01), Jones et al.

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