Electrical computers and digital processing systems: processing – Processing control – Processing control for data transfer
Reexamination Certificate
1999-11-15
2002-12-31
Treat, William M. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Processing control for data transfer
Reexamination Certificate
active
06502187
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a pipelined computer, and more particularly to a pipelined computer executing variable-length data-handling instructions.
One of the known techniques for this is, for example, a method for executing load instructions repeatedly to implement variable-length data-handling instructions while checking data lengths on a micro instruction level. For example, assume an instruction pipeline such as the one shown in FIG.
8
.
An instruction supply unit
1
analyzes a software instruction fetched from main storage or instruction cache memory (not shown in the figure) and supplies a micro instruction corresponding to the software instruction. At this time, the instruction supply unit
1
appends an identifier (hereafter called “micro tag”) to the micro instruction to identify it.
A register rename unit
3
checks if there is a register hazard (conflict) between the micro instruction sent from the instruction supply unit
1
and the preceding micro instructions. If necessary, the register rename unit
3
renumbers the resource register (register renaming) to prevent the register hazard.
A reorder buffer
4
stores therein the micro instructions sent from the register rename unit
3
until execution of the stored micro instructions are completed. The reorder buffer
4
also has two fields for each stored micro instruction: one is a field where the execution result of the stored micro instruction is stored and the other is a field where a flag indicating whether the execution of the stored micro instruction is completed is stored. Based on the contents of the execution completion field, the execution results of the completed micro instructions are written into software visible registers in the order in which the execution results were stored in the buffer (hereinafter, this write processing is called “graduate”). Upon completion of storing the execution result into the software visible register, the registered entry is released and the processing of the micro instruction is completed.
A reservation station
5
stores therein the micro instructions sent from the reorder buffer
4
. A check is made for the resources to be used by the micro instructions in the buffer. Micro instructions whose resources are made available are sent sequentially to an execution unit
6
for execution. That is, from the reservation station
5
, the micro instructions are sent to the execution unit
6
for execution, not in the order in which they were issued, but in the order in which required resources are made available.
The execution unit
6
executes a micro instruction received from the reservation station
5
. When the execution of the micro instruction is finished, the execution unit
6
sends the execution result and execution completion notification to the reorder buffer
4
to inform that the micro instruction has been completed.
FIG. 9
is the timing diagram of the instruction pipeline shown in FIG.
8
. In the description below, assume that the system comprises one load/store unit, one register operation unit that performs register-to-register operation, and one branch unit. Assume that, from the time the instruction is fetched from memory to the time the execution result of the instruction is written into reorder buffer
4
, the load store unit requires nine stages, the register operation unit requires seven stages, and that the branch unit requires six stages. Also assume that up to four instructions may be stored in the reorder buffer
4
at the same time and that up to four instructions may be graduated from the reorder buffer
4
.
In
FIG. 9
, a micro instruction loads data from memory while calculating the data length. Each time the load instruction (load) loads data from memory, the subtraction instruction (sub) subtracts the length value of “8” from the data length to calculate the remaining data length. The branch instruction (bra) checks this remaining data length and, when it becomes “0” or smaller, ends the variable-length data processing and executes a branch. This operation is repeated for the maximum length of variable-length data. The and instruction is used to wait for the condition to be satisfied.
The four micro instructions fetched in T
1
are register-renamed in T
2
and stored in the reorder buffer
4
in T
3
. The micro instructions are stored in the reservation station
5
in T
4
and then sent to the execution unit
6
in T
5
. The bra instruction at instruction (
3
) is put in the wait state in the reservation station
5
to check the execution result of the preceding sub instruction at instruction (
2
). In T
6
, when the execution result of the sub instruction at instruction (
2
) is determined, the bra instruction is sent to the branch unit.
When the bra instruction at instruction (
3
) sent to the branch unit detects that the operation result of the sub instruction at instruction (
2
) is “0”, it fetches an instruction at the branch destination in T
8
. The and instruction at instruction (
7
), which is the instruction at the branch destination, is fetched in T
8
and graduated in T
15
.
Because the conventional method described above performs data processing while checking the data length with the use of micro instructions, there are more pipe stages as the operation clock speed increases. Therefore, when a branch is “taken”, it takes long to fetch the target instruction at the destination address. This means that, even if the operation clock speed is increased, the instructions require more clocks if there are many branch instructions, making it difficult to enhance instruction performance in proportion to the clock speed.
SUMMARY OF THE INVENTION
The present invention seeks to solve the problems associated with the prior art described above. It is an object of the present invention to provide a pipelined computer which is capable of handling variable-length data without having to use branch instructions and which increases the speed of a variable-length data-handling software instruction.
According to one aspect of the present invention, the pipelined computer according to the present invention comprises an instruction division unit which divides a variable-length data-handling instruction into a predetermined number of fixed-length data-handling instructions; and an execution unit which executes said fixed-length data-handling instructions, received from said instruction division unit, in a sequence of generation during the division.
REFERENCES:
patent: 4103329 (1978-07-01), Davis et al.
patent: 5404473 (1995-04-01), Papworth et al.
patent: 5822602 (1998-10-01), Thusoo
patent: 5828875 (1998-10-01), Halvarsson et al.
patent: 6032252 (2000-02-01), Petro et al.
patent: 59-22142 (1984-02-01), None
patent: 1-318118 (1989-12-01), None
patent: 2-189633 (1990-07-01), None
patent: 5-265755 (1993-10-01), None
“Interface”, CQ Publishing, Issue No. 249, Mar. 1, 1998, pp. 99-131, In Japanese.
NEC Corporation
Sughrue & Mion, PLLC
Treat William M.
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