Peak power reduction when updating future file

Electrical computers and digital processing systems: processing – Processing control – Context preserving (e.g. – context swapping – checkpointing,...

Reexamination Certificate

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Reexamination Certificate

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07124285

ABSTRACT:
In one implementation, a programmable processor is adapted to include a first set of registers and a second set of registers. The first set of registers may have a future file, and the second set of registers may be architectural registers. Following a termination of an instruction in the processor, the future file may be restored with values in the second set of registers. The future file is restored over more than one clock cycle.

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Translation of Feb. 2, 2005 Office Action in Taiwan prosecution of Application No. 091105736.

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